Second-level Cache Organization for Data Prefetching

This paper studies hardware prefetching for second-level (L2) caches. Previous work on prefetching has been extensive but largely directed at primary caches. In some cases only L2 prefetching is possible or is more appropriate. We concentrate on stride-directed prefetching and study stream buuers and L2 cache prefetching. We show that proposed stride-directed organizations/prefetching algorithms do not work as well in L2 caches and describe a new stride-detection mechanism. We study an L2 cache prefetching organization which combines a small L2 cache with our stride-directed prefetching algorithm. We compare our system with stream buuer prefetching and other stride-detection algorithms. Our simulation results show this system to perform signiicantly better than stream buuer prefetching or a larger non-prefetching L2 cache without suuering from a signiicant increase in the memory traac.